1. Field of the Invention
The present invention relates generally to integrated CMOS transistor logic circuits, and more particularly to a form of such logic circuits which permits the use of larger power supply voltages for generating output signals of greater magnitude while retaining high density advantages of low-voltage CMOS processing.
2. Description of the Related Art
CMOS is the most widely used technology for integrated circuits today. The electrical properties of CMOS technology are well understood. The voltage that can be used to power CMOS circuits is dependent upon the physical dimensions of the individual transistors (i.e., their geometry) and the particular processing utilized in the manufacturing of the transistors.
Many CMOS integrated circuits can be operated at power supply ranges of 5 volts or less. Processing techniques have been developed and are known to those skilled in the art for producing highly-dense CMOS integrated circuits which operate over a 5 volt power supply range. These integrated circuits produce output signals which also range approximately between ground and +5 volts.
However, in many cases, the CMOS integrated circuit must drive or control some other device which requires an input signal having a larger voltage magnitude. One example is the need to drive liquid crystal displays (LCD) of the type used in hand-held games, hand-held computers, and laptop/notebook computers. LCD displays used in computer screens require a large number of input control signals which must operate at voltages from 8 volts to as high as 20 volts. If the CMOS integrated circuit is going to be capable of generating an output signal having such an increased voltage magnitude, then the power supply range for such CMOS integrated circuit must also have an increased voltage magnitude.
In general, the higher the power supply voltage needed, the larger the individual transistors must be; in addition, the use of larger power supply voltages necessitates special processing considerations. Larger device geometries and more complex processing generally result in higher manufacturing costs for a particular integrated circuit, since the total area of the integrated circuit, and the complexity of the manufacturing process, are both major factors in determining the cost of a particular circuit.
There are several mechanisms which limit the voltage that a particular CMOS transistor can tolerate. The three most critical mechanisms are:
a) channel breakdown due to excessive voltage appearing between the source and drain terminals of the CMOS transistor. PA1 b) dielectric breakdown of the gate oxide, which is a destructive mechanism. This particular failure mechanism can also be a long term reliability problem because it has been shown that breakdown of the gate oxide is both time dependent and voltage dependent. PA1 c) junction breakdown corresponding to the reverse voltage breakdown of the diode which appears at the source and drain of all CMOS transistors.
With respect to the failure mechanism of junction breakdown, there are actually two types of junctions in a standard CMOS integrated circuit that can breakdown, namely, the source/drain to well junction, and the source/drain to substrate junction. Of these two types of junctions, the source/drain-to-well junction will typically have the lower breakdown voltage and must be considered to be the worst case. Assuming that an n-well process is used, then the lower breakdown voltage is generally in the p channel transistors; conversely, if a p-well process is used, then the lower breakdown voltage occurs in the n channel transistors.
In a typical CMOS logic gate circuit, one or more n-channel devices are coupled between a ground power supply conductor and an output node. In addition, one or more p-channel devices are coupled between the output node and the VDD power supply conductor. When the n-channel transistors are enabled, they create a conductive path from the output node to ground. Alternatively, when the p-channel transistors are enabled, they create a conductive path from the output node to positive supply voltage conductor VDD. Thus, the output node of the logic gate switches between ground and VDD. The gate terminals of the various transistors are coupled to an external input terminal, or alternatively to an output node of a previous logic gate circuit.
In the standard CMOS logic configuration briefly described above, the gate oxide of all the transistors will see a voltage equal to the difference in the power supplies (VDD-GND). In addition, the voltage across the channel, i.e. the voltage between the drain and source, for each of such transistors will also be the difference in the power supplies (VDD-GND). The voltage across the gate oxide, and the voltage across the channel, will not always be at the maximum difference between the power supply voltages, but there is a state of the inputs which can force any of the transistors to see the maximum power supply voltage differential across the gate oxide or across the channel. Accordingly, the power supply voltages for these standard CMOS logic configuration must be chosen to prevent the occurrence of either gate oxide breakdown, impaired reliability of the gate oxide, or channel breakdown.
In addition, the junction diodes formed at the source and drain of each of the CMOS transistors in a standard logic gate will also be exposed to the maximum supply voltage differential as a reverse bias on such junction diodes. Therefore, the magnitude of the voltage of power supply VDD relative to ground cannot exceed the reverse bias junction breakdown of such devices; as indicated above, the worst case normally is observed in the source/drain-to-well junction.
As has been noted above, gate oxide breakdown is partly time-dependent, and the long term reliability of a CMOS integrated circuit is severely affected by the maximum gate oxide voltage applied to the CMOS transistors included therein. Even if the supply voltages are maintained below the theoretical gate oxide breakdown voltage, the long-term reliability of an integrated circuit using such standard CMOS logic configurations can be reduced if the maximum gate oxide voltage is permitted to be too high.
In view of the foregoing, it is an object of the present invention to provide CMOS integrated circuit transistor configurations which can be operated over a power supply range significantly exceeding 5 volts in magnitude (i.e., a higher voltage range) while still using CMOS transistor geometries, and CMOS processing techniques, which are conventionally used for CMOS integrated circuits that operate over a standard 5 volt power supply range.
It is another object of the present invention to provide CMOS integrated logic circuits which permits the use of larger power supply voltages for generating output signals of greater voltage magnitude while retaining high density advantages of low-voltage CMOS processing.
It is still another object of the present invention to provide CMOS integrated circuit transistor configurations which use low-voltage type CMOS transistors in conjunction with higher-voltage power supply ranges while preventing channel breakdown, gate oxide breakdown, and junction breakdown failure modes.
A further object of the present invention is to provide such CMOS integrated circuit transistor configurations which use low-voltage type CMOS transistors in conjunction with higher-voltage power supply ranges without impairing the reliability of such integrated circuits.
A still further object of the present invention is to provide such CMOS integrated circuit transistor configurations which use low-voltage type CMOS transistors in conjunction with higher-voltage power supply ranges without significantly increasing the cost of manufacturing such integrated circuits.
These and other objects of the present invention will become more apparent to those skilled in the art as the description of the present invention proceeds.